PDH(Plesiochronous Digital Hierarchy) 碼框架構

F

F

F

Frame #1

CH 1

(8 bits)

125 u sec

CH 2

(8 bits)

CH 24

(8 bits)

• D4/Super Frame(SF)

Frame #2

Frame #6

F

Frame #12

A for Frame #6

B for Frame #12

• Rate(DS1) = (1+8 x 24) / 125 usec = 1.544 Mbps

• Rate(E1) = 64 x 32 = 2.048 Mbps

CH 1

(8 bits)

CH 2

(8 bits)

CH 24

(8 bits)

• AD4/Extended Super Frame(ESF)

A for Frame #6

B for Frame #12

C for Frame #18

D for Frame #24

F

F

F

Frame #13

125 u sec

Frame #14

Frame #18

F

Frame #24

12 framing bits for sys.

6 framing bits for sys.

6 for CRC

12 for data link

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